iic testbench
`timescale 1ps/1ps `define TBCLK 20000 module tb_peri_top; genvar k; integer i, j, d; reg ck50m = 1; always #( `TBCLK /2 ) ck50m = ~ck50m; reg reset=1; wire sda; wire scl; pullup (sda); pullup (scl); reg [3:0] act_iic=0; iic_unit inst_iic_unit ( .reset ( reset ), .sclk ( ck50m ), .address ( 8'h11 ), .command ( 8'h91 ), .data_low ( 8'h0 ), .data_high ( 8'h0 ), .action ( act_iic ), .sda (sda), .sc..
iic master
module iic_unit ( input reset, input sclk, input [7:0] address, input [7:0] command, input [7:0] data_low, input [7:0] data_high, input [3:0] action, inout sda, inout scl ); parameter ST0 = 0, ST1 = 1, ST2 = 2, ST3 = 3, ST4 = 4, ST5 = 5, ST6 = 6, ST7 = 7, ST8 = 8, ST9 = 9, ST10 = 10, ST11 = 11, ST12 = 12, ST13 = 13, ST14 = 14, ST15 = 15, ST16 = 16, ST17 = 17, ST18 = 18, ST19 = 19, ST20 = 20, ST2..
iic slave model
module slave_iic ( input reset, input sclk, inout sda, inout scl ); parameter ST0 = 0, ST1 = 1, ST2 = 2, ST3 = 3, ST4 = 4, ST5 = 5, ST6 = 6, ST7 = 7, ST8 = 8, ST9 = 9, ST10 = 10, ST11 = 11, ST12 = 12, ST13 = 13, ST14 = 14, ST15 = 15; parameter IDLE = 0, START = 1, STOP = 2, WR_DH = 3, WR_DL = 4, MYACK = 5, RCV_ACK = 6, RCV_NACK = 7; wire addr_field; wire i2c_sss; wire i2c_ppp; reg [6:0] SM_SADR;..
